This invention relates to a power reset signal generator, and more particularly, to a power reset signal generator suitable for power application to an electronic circuit.
Electronic systems typically include a power reset circuit that generates a reset signal when the power applied to the system is either initially turned on or cycled from being turned off and then turned on. The electronic system uses the power reset signal to initialize various subsystems at power up. Because the power reset circuit is occasionally used, portable electronic systems typically require a low current draw for the power reset circuit in order to conserve battery power.
Manufacturers typically test electronic systems under controlled test conditions, which includes power reset testing. These controlled test conditions typically include a slow ramp time for the applied power. However, in user systems, the user frequently plugs the electronic system into an already powered system, and this provides what is commonly called xe2x80x9chot plug inxe2x80x9d. In such hot plug in situations, the power signal has a fast ramp time. Accordingly, devices that the manufacturer has tested under controlled conditions may fail in the field.
The present invention provides a power reset signal generator that is independent of the ramp time of the applied power. The present invention also provides a power reset signal generator that draws low current.
The present invention provides a power reset signal generator that includes a first voltage divider that provides a first reference signal in response to an applied power signal having a ramp time. The first reference signal is substantially equal to the voltage of the applied power signal for at least a portion of the ramp time in the event that the voltage of the applied signal is less than a threshold voltage and is substantially proportional to the voltage of the applied power signal in the event that the voltage of the applied signal is greater than the threshold voltage. The power signal generator also includes an inverter coupled to the output of the first voltage divider, and includes a second voltage divider having a first input coupled to an output of the first voltage divider, having a second input coupled to the output of the inverter, having an output for providing a reference signal. An NAND gate has a first input coupled to the output of the first voltage divider, a second input coupled to the output of the second voltage divider and an output for providing a power reset signal in response to the first and second reference signals.
The power reset generator may include a capacitor coupled to the second input of the second voltage divider for maintaining the voltage on the reference signal at a predetermined voltage level for a predetermined time. The pulse width of the power reset signal may be the greater of the predetermined time and a time of the voltage level of applied power signal becoming greater than the threshold voltage.